Free-RAM

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Introduction

The Free-RAM core is a simple, portable, and parameterized RAM useful for many applications.  It's key features are:

Dual Port RAM and many types of FIFO's included.

Portable -- A portable RAM core is essential for writing VHDL code that can work on many types of FPGA's and ASIC's.  It has been ported to Xilinx Foundation, Altera Quartus, and ModelTech ModelSIM platforms.  Other platforms will be added.  

Parameterized -- The same entity can be used for any size of RAM.

Automatically uses the most appropriate RAM for the target device (I.E., in a Xilinx Virtex it will automatically switch between LUT based RAM's and Block Select RAM's).

100% VHDL design makes code management much easier (I.E., version control software, archiving, etc).

Current Version

The current version of the Free-RAM core is v0.6.  New to this version is:

ram_dp2 component added, with two independant ports with both read/write abilities.

Changes from v0.4 to v0.5

Better compatability with the Xilinx Unisim package.

Size and speed optimizations for fifo_xxcount.

Minor bug fixed in fifo_rdcount.

Device Dependant Notes

Xilinx Foundation

Currently, if a RAM block is less than 2 kbits it will be implemented with LUT's.  RAM's of 2 kbits and larger will be made using the Block Select RAM of the Virtex and Spartan-II series of FPGA's.  This can be overwritten using the block_type flag.

Since the Virtex/Spartan-II Block Select RAM only has synchronous read ports, all async-read port RAM's will be made using LUT's.

This core works with chips other than the Virtex, although care should be taken when making RAM's of larger than 2 kbits.

There is a bug in the Xilinx Foundation simulator.  The RAM may fail to simulate properly if using the functional simulation mode.  It appears to work properly when using the timing simulator.

The ram_dp2 component is implemented with Block Select RAM's only-- no LUT based RAM's.  

Altera Quartus

This library creates RAM using the embedded system blocks.  

Since Quartus only supports the APEX line of parts, this library has only been tested in those.

There is a bug in the Altera Quartus simulator.  It appears that with some RAM configurations using the functional simulation mode the test bench will fail.  This doesn't happen when using the timing simulation mode.

Quartus must be set to use the VHDL-1993 specification.  Do this by selecting Project/General_Settings from the menu and clicking on the VHDL Input tab.  From there, select VHDL 1993.

Currently the ram_dp2 is not supported for Altera

Model TECH ModelSIM

See the Free-IP FAQ regarding special ModelSIM settings.

Other Platforms

While the Free-RAM core hasn't been tested on other platforms, there are a couple that it might work fine on.  Specifically:

Altera MAX II+ might work with the Free-RAM core (Quartus version).  

Synplify, from Synplicity, might work with the ModelSIM version of the RAM core.  

 

Tips & Tricks

Writing portable VHDL code that takes full advantage of the target architecture is difficult and often filled with compromises-- and RAM is no different.  Here are some tips and tricks that will help you use the Free-RAM core effectively.

Use synchronous reads, especially on larger (>1kbit) RAM's.  This helps with timing issues and makes it possible to use the Xilinx Virtex Block Select RAM's.

Don't read and write to the same location at the same time.  This may result in undesired effects.  At the very least the read could give bad data, but depending on the target device it could result in a bad write.

Optimize the RAM size for the expected device, but keep in mind other devices as well.  The Altera Apex 20K devices has 2kbit RAM blocks, while the Xilinx Virtex has 4k bit blocks.  But also remember that Altera Apex devices don't have any small RAM blocks (a.la., Xilinx LUT's).

Support

Use the Free-IP mailing list for support.  If this doesn't work for you (for whatever reason) send us email.

 

© 1999-2000, The Free-IP Project.  This page was last updated on July 18, 2000 10:43 PM.