IntroductionThe ram_dp2 component is a full dual port RAM. Unlike the original ram_dp component, ram_dp2 has two ports which are capable of both reads and writes (ram_dp has one write-only port and another read-only port). Of course, this ability comes at a price-- portability and flexability. The ram_dp2 component is not as portable as the basic ram_dp, and it does not offer as many options. Component DeclarationThe basic component declaration of the Free-RAM dual port module is: component ram_dp2 generic (addr_bits :integer; data_bits :integer; block_type :integer := 0); port (reset :in std_logic; p1_clk :in std_logic; p1_we :in std_logic; p1_addr :in std_logic_vector (addr_bits-1 downto 0); p1_din :in std_logic_vector (data_bits-1 downto 0); p1_dout :out std_logic_vector (data_bits-1 downto 0); p2_clk :in std_logic; p2_we :in std_logic; p2_addr :in std_logic_vector (addr_bits-1 downto 0); p2_din :in std_logic_vector (data_bits-1 downto 0); p2_dout :out std_logic_vector (data_bits-1 downto 0) ); end component;
Generic MapThe generic portion of the component has parameters for the number of address and data bits, plus flags to specify read modes and optimization hints. The parameters are:
Note that the ram_dp2 component doesn't have a register_out_flag. The ram_dp2 operates only with synchronous reads. Also note that while the block_type is defined, it is not currently used. The Free-RAM core will always use the most appropriate RAM type. Port MapAside from the common reset signal, the ram_dp2's two ports are identical so we'll only describe one:
Read and Write TimingThe read and write timing is identical to the ram_dp component (assuming that register_out_flag=1). |
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