Archive for the ‘Articles’ Category

Review Of On Line Printed Circuit Board ( PCB ) Manufacturing Services

Thursday, November 19th, 2009

The good old days

In the good old days the options available for the hobbyist to make PCB s were limited to various self etch systems. If you played with PCBs, you kept quantities of fairly noxious chemicals around the house, got moaned at leaving brown ferric chloride stains in the sink and got used to having the finger colour of a heavy smoker. Good quality PCBs were out of reach of most, due to the high cost involved in the manufacture of small quantities of PCBs.
Also etching your own PCBs limited the number of layers in the PCB to just two and that was a difficult and long winded process. Plus you didn’t get the niceties such as a silk screen or the necessities like a solder mask.
Come forward to now. Several companies have come up with offerings for the gifted amateur or the small business to manufacture good quality PCBs at reasonable prices in numbers down to just one. The low cost is achieved by sharing the production costs amonst many buyers. Having used these companies there is no way I would want to return to the good old days.

PCB Cost sharing Systems

So how does it work – well the problem in the old days was the NRE – that’s Non Recurring Engineering cost or set up charge. The PCB manufacturer would charge a fixed ( large ) fee to setup his production facility to make your board. If you are making loads of boards the cost is spread, if your making only one board the cost was usually prohibitive.
The idea now is that the PCB manufacturer accepts designs of a similar type – same layer count and board thickness etc. – from many customers. All the designs are then placed in to one big PCB. The big PCB is then made and split up into each customers requirement. Each customer is charged for the area of PCB used. There is still a setup charge, but the cost is spread amongst all the customers.
The disadvantage of this approach is that if you want to repeat the order you pay again for the setup charges.

Technical Specifications

There are now many companies on the Internet who offer these services. The range of product offerings is sufficient for most, ranging from simple single layer PCBs, upto complex 6 layer beasts. All the companies I use provide these facilities in the basic price :
unlimited drill sizes.
unlimited numbers of holes.
complex board shapes.
solder mask.
silk screen.
Minimum trace widths = 0.15mm ( 6 mil )
Minimum hole diameter = 0.3mm ( 12 mil )
All the PCB companies offer extended technical specifications such as blind/buried vias, micro vias, gold plating at extra cost.


Generally the PCBs are priced on the quantity of material used. It is worth checking the prices across several companies, as they have different pricing structures. There are cost estimators on all the web sites which allow for easy price comparison.

Where can I get this done ?

This is a list of the companies I have used offering a shared PCB service to individuals and to companies. I’m deliberately only considering EU based companies as it makes the customs and excise stuff much easier to handle. You don’t get any nasty surprises when the goods arrive.


These are my current go to PCB manufacture.

Very professional and a large range of options available at very competitive prices, plus a fast turn quote system for PCBs that don’t fit into the web based options – like proper controlled impedance designs.


Setup to handle the hobbyist as well as professional markets. The big plus for the hobbyist is the number of different file formats that can be used. They will accept design files from many different PCB layout tools, gcpreview files , as well as industry standard Gerber (RS274-X) . It is worth checking that both your PCB tools and version are supported before using this bit of service though. They also provide a free PCB pool version of TARGET 3001 PCB layout software.

Offer a range prototype PCBs
1 to 6 layers in standard 1.6mm thick FR4.
any shape pcb as standard.
PCBs are priced purely on the quantity of PCB used, with a minimum area of 1dm2 .( that’s a PCB 100mm by 100mm).
Other build options are available on request.

Also PCB_POOL will provide a Free Laser SMD stencil with prototype orders – which is ideal if you have bought the PCB-POOL reflow oven.

Accept a full range of credit cards.


Example Board

Now doing a range of 3D printed products and metal front panels designs.


They are more aimed at the professional prototype market and will only accept data in Gerber (RS274-X) format. The shared PCB concept is slightly different here, in that here you have to catch a ‘train’. Each train is a PCB type, for example 4 layer 1.6mm is a train. Trains depart on different days of the week. Popular trains leave everyday, less popular maybe only once a week. All the delivery times are from when a train leaves not when the order is placed.

Offer a wide range of products :
1.6mm FR4 (upto 6 layers )
0.8mm FR4 ( to 2 layers )
flexible PCB ( to 2 layers )
any shape pcb as standard.

Prices are a mix of setup charge and area, an on line estimator is available.
Minimum board size is 10mm x 10mm.
Other build options are available on request.
PCB assembly is also available. ( which is very useful if fine pitch SMD devices or BGAs are being used)
Accept a full range of credit cards.


Example Board

Direct Digital Synthesis (DDS) For Idiots ( like me )

Thursday, November 19th, 2009

Other names are :
DDFS: Direct Digital Frequency Synthesis:
NCO: Numerically Controlled Oscillator


DDS is a method of generating timing signals from a clock source with programmable frequency. It is used in all sorts of places such as frequency hopping, signal synthesis, medical imaging systems, radio receivers, PLLs, test equipment, the list goes on and on. The DDS structure was first proposed in 1971 by Tierney, Josepf, Charles Rader, and Bernard Gold, “A digital frequency synthesizer,” IEEE Transactions on Audio and Electroacoustics.

I have used DDS in a number of places and have found it an easy design, especially for a digital head like me, as the basic DDS much simplifies the analog section of the design. My first design using this technique was an 8 channel audio sinewave generator. One 30k gate FPGA controlled the all 8 of the channels and 4 CODECS did the rest. The performance was excellent – frequency range from 0-20kHz in sub 0.5Hz steps, S/N of better than 90dB and channel separation of better than 90dB. All channels operated independently and were programmed via a USB link to a PC.

What follows is the stuff I find useful when designing a DDS based system. There is much much more that is possible.

Basic DDS Design


Drawing 1 Basic Vanilla DDS

The basic method works as follows: ( see Drawing 1 Basic Vanilla DDS) The phase register is loaded with a value which is proportional to the required frequency. See Equation 1 Output Frequency.

Then at each rising clock edge the phase register is added to the accumulator.

After enough clocks and additions the accumulator rolls over and starts again from the remainder. That’s all there is for the Numeric Control bit, the rest is output formatting. The top p bits of the accumulator are used to address a lookup table. The lookup table outputs q data bits to the DAC. Which generates the analog output. The anti-a aliasing filter removes all the lumps and bumps, and is fixed at around a third the clock frequency.

Some Basic DDS Equations

See Drawing 1 Basic Vanilla DDS

dds_output eqn

Equation 1 Output Frequency

where :

n is the number of accumulator bits

Frequency Resolution or what happens if I add one to the phase register

dds_resolution eqn

Equation 2 Frequency Resolution

where :

n is the number of accumulator bits

With accumulator sizes of 32 bits or it is easy to get resolutions smaller than 1/2 Hz, even at high frequencies.

Max frequency

dds_max eqn

Equation 3 Maximum Frequency

where :

m is the number of phase bits

n is the number of accumulator bits

For reasons of practical output filter design, the maximum output frequency is normally limited to Fclk/3. This is so that the max frequency is within the lower passband of the of output anti-aliasing filter. At higher frequencies the signal gets distorted as the output filter peaks before transitioning into the stop band.
If perfect filters were available Fclk/2 would be usable.

Max Phase Jitter

The phase jitter is basically determined by the frequency of the system clock. Although it can be reduced by a neat trick in the analog domain.


Equation 4 Phase Jitter

Signal to quantization noise (SQR )

This is basically a function of how many many bits the DAC has and how much of the range is used.

dds_noise eqn

Equation 5 Quantisation Noise

where :

q = number of bits in the DAC signal is the current signal output level and Max Signal is the full scale output of the DAC.

Over sampling

Oversampling is the use of higher than required sample rates. Minimum rate is defined by Nyquist at 2x the required output frequency, any rate above that is oversampling. Can be used to reduce the effects of quantization noise. Oversampling reduces the effects of quantization noise because quantization energy is spread equally across the bandwidth of the output DAC. By only using a proportion of the the output bandwidth, the quantization noise in the required band is reduced.

dds_oversample eqn

Equation 6 Reduction in Quantisation Noise due to Oversampling

where :

q = number of bits in the DAC signal is the current signal output level and Max Signal is the full scale output of the DAC.

Accumulator Truncation

Errors are added to the output signal due to the truncation of the accumulator before the look up table. Causes spurs in the frequency domain at multiples of the output frequency. Spurs vary from 0 to maximum truncation error shown below.

Assume accumulator is n bits.

Look up table address is p bits

If n – p is >=4 then

dds_truncation eqn

Equation 7 Truncation Errors

Other Error Sources

There are a number of other sources of errors and noise in a DDS system. Some are outlined below.

DAC linearity
Basically this is a measure of whether each increment of the digital data causes a consistent increment in the analog output.

DAC switching transients
All DACS show a step response when the input digital data changes. This causes switching transients to appear on the output.

Clock feed through.

This will mainly be down to power supply and layout issues. Take care to provide enough decoupling on the power supplies to all the devices and that the PCB layout is sympathetic to getting low noise analog outputs.

Some other stuff to know

Clock Jitter – reduced by switching to the analog world then back to digital!!
Rather neat this – a DDS can reduce the jitter from the base clock frequency. The incoming clock will have a jitter component, this shows up in the output signal as a frequency components above the fundamental of the required output. By filtering these jitter components to say 50dB below the required fundamental frequency, the jitter component in the output is reduced.

Lookup Table considerations
If used for sinewave generating then the lookup table can be shortened, as a sinewave is four way symmetrical. So the table only needs to store a single quadrant of data, then with a bit of simple data manipulation all values can be found. This reduces the lookup table requirements by a factor of 4. So we can have either a smaller table or have more resolution.

The lookup table needs to be accessed at the system clock rate.

Could use interpolation to improve the resolution of a lookup table.

Lookup tables can be designed out completely by the use of various techniques such as CORDIC or the Taylor series. This is a bit beyond the scope of this introductory article though.

DAC and Analog Stages
The main thing about the DAC is the update rate must cope with the system clock speed not the required output frequency. This is the main limitation of a DDS system.

The analog stage is easily designed as the system clock is at least three times the required output frequency. Also compared to other signal generation techniques the system clock frequency is constant. Thus much simplifying any filter design for the output stage.

Easy things you can do with a DDS

Frequency Shift Keying (FSK ) /Frequency Modulation (FM)/Frequency Hopping
Changing the phase register changes the frequency. So FSK can be implemented by simply changing the phase register between two values.

Alternatively two phase registers can be used with a multiplexer to select the register which is used. More sophisticated versions would allow for a gentle change between two or more values, possibly under microprocessor control. Or using a table of values to implement a frequency hopping system.

The speed of change is basically down to how fast the phase register can be altered.

Changing the frequency does not affect the phase of the output signals.

The big advantage is that the frequency change creates no discontinuities in the output waveform.

Frequency Sweep
Very similar to the FSK system, by making phase register the output of a clocked counter, the output frequency can be made to sweep at the rate of the sweep clock. With the advantages of no phase shifting or discontinuities on change.


Drawing 2 DDS System With Frequency Sweeping

PSK Phase shift Keying
Adding a fixed offset to the output of the accumulator is the equivalent to adding a fixed phase offset. By changing the amount added the phase of the output signal is varied. This can be done as using a simple register or multiple registers or look up tables.

Gives excellent phase shift resolution.


Drawing 3 DDS with Phase Modulation

Phase Dithering To Reduce SFDR Whats SFDR ? It’s the spurious free dynamic range.

It is a measure of the power of the required frequency against the power of the largest noise source in the signal. Typically this noise is at a frequency multiple of the required frequency.

By using the techniques described in the phase modulation, you can trade over system noise performance against SFDR. Basically by adding a small amount of random phase noise to the DDS system, the coherence of the noise signals is reduced. This can reduce the SFDR by upto 12dB.

Amplitude Modulation (AM )
Can be done digitally by implementing a digital multiplier, after the lookup table, or in analog fashion by manipulating the gain of the output signal.

Beware though if implemented digitally, the DAC won’t be used over its full operating range at all times. Thus the SQR figure will vary depending on the amplitude.

Also the multiplier will need to run at the same frequency as the accumulator, which may restrict the maximum frequency the DDS can run at. ( Note some FGPAs now include hardware multiplier blocks which make this much easier to implement. )

Some other ways of AM modulating the signal are :

  • use a multiplying DAC.
  • change the DAC reference voltage dynamically.
  • use an analog switched attenuation stage.

Arbitrary Function Generator
If the lookup table is filled with values from an arbitrary periodic waveform, then the output will be that waveform at the required frequency. This may need a higher specification DAC and analog stage.

Implementing DDS systems

There are numerous ways of implementing a DDS. There are discrete DDS ICs available, it is a easy shoe into an FPGA and it can even be done in software. My favourite is the FPGA route, just for the flexibility it gives. Several of the FPGA vendors supply DDS IP, but I find it just as easy to roll my own. See below for some simple sample VHDL code.

Simple VHDL Implementation
— following code will output a binary ramp or sequential values from a lookup table at a frequency – proportional to the value in the phase reg.
— the signal ramp selects the ramp output or the sinewave output.
library ieee;
use ieee.std_logic_1164.all;

entity dds is
clk : in std_logic;
reset : in std_logic;
phasereg : in std_logic_vector( 27 downto 0 );
ramp : in std_logic;
data : out std_logic_vector( 11 downto 0 )
end entity dds;

architecture rtl of dds is

component lookuptable is
clk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector( 11 downto 0);
data : out std_logic_vector( 11 downto 0)
end component lookuptable;

signal accumulator : std_logic_vector( 31 downto 0 );
signal iphasereg : std_logic_vector( 31 downto 0 );
signal lookuptabledata : std_logic_vector( 11 downto 0 );


— this just makes the math a bit easier to look at later on.
iphasereg <= x”0″ & phasereg;

— process adds phase reg to accumulator every clock – the basic oscillator part of the dds.
l_dds : process ( clk, reset, i_phase_reg, accumulator)
if ( reset =’1′ ) then
accumulator <= x”00000000″;
if (rising_edge(clk) ) then
accumulator <= accumulator + i_phase_reg;
end if;
end if;
end process;

— select either a ramp waveform or data from the lookuptable.
data <= accumulator (31 downto 20 ) when ramp =’1′

— instantiate the lookup table
— assumes a 4096 entry lookup table with each entry being 12 bits wide.
— adjust values to suit
— typically would fill with sinewave values – but could be any periodic waveform.
— best if synchronous
l_lookup_table: lookuptable
( port map
clk <= clk,
reset <= reset,
addr <= accumulator( 31 downto 20 ),
data <= lookuptabledata
end architecture dds;

Linkages and further reading

DDS links
Altera IP based DDS
Analog Devices Web site for discrete DDS ICs
Analog Devices Tutorial
EDN Article On DDS
Jesper’s AVR pages – MiniDDS – DDS in software.
Xilinx Frequency synthesis App Note

Andraka’s CORDIC in FPGAs
The maths involved or – “Fixed Point Trigonometry with CORDIC Iterations” by Ken Turkowski
Open Cores Implemenatation

Designing FPGAS In VHDL On A Budget

Thursday, November 19th, 2009


FPGAs or Field Programmable Logic Arrays to give them their full name, are large lumps of uncommitted logic. The field programmable bit gives the clue to their usage and utility. This basically means that on their own their don’t know what to do, they have to be programmed and that generally happens once they have been stuck down to the PCB. FPGAs are the logic equivalent of the EPROM/FLASH in the processor world.

Back in the good old days FPGAs were the domain of big corporates, due to the high price of silicon and the exorbitant price of design tools. Fortunately the world is now different and FPGAs and design tools are available for every size of pocket.

Why Use FPGAs?

Because they are cool.

Because they make PCB layout less risky, as changes to the design can often be accommodated in the FPGA.

Because in a commercial environment they enable the PCB layout to proceed earlier.

Because things can be done in an FPGA that are impossible in discrete logic due to physics and signal integrity issues.

Because they provide design security. It is much more difficult to reverse engineer an FPGA design than a design in discrete logic.

Because they are a cheap option.

Because they are very dense compared to standard logic.

Because they use less power than the discrete equivalent.

Because it looks good on the CV.

Because I can’t afford to make ASICS.

Because there are lots of existing designs to re-use. Design re-use either through your own developed libraries or through external IP allows for fast design times.

Brief History Of FPGAs

FPGAs have grown out of an older technology called PLDs. Programmable logic arrays. These where basically small devices of up to 24 pins which contained an array of similar gates. The early devices typically contained AND gates for outputs, and the user programmed which of the inputs got used in each AND gate. The idea took hold and developed with the addition of flipflops and more internal stuff.

Now modern FPGAs have thousands of flip flops, million gate capacity, internal RAM, PLLs, DSP blocks, fancy interfaces and run internally at really whizzy speeds like 500MHz.

All the technologies use a loads of programmable switches to route signals and configure functionality with the device. The switch can be FLASH, SRAM or ANTIFUSE based. Of the three technologies for implementing FPGAS, FLASH and SRAM based dominate. ANTIFUSE technology is generally used only for specialist stuff, like radiation hardened for space and mission critical stuff.

The basic Array is made of FLASH based cells. This means the device is non volatile, it remembers the program when it is powered down. Typically FLASH is less dense that the other options. It can be programmed in circuit.

The logic array is based on SRAM cells. These are definitely volatile so the program has to be downloaded every time the power is applied. There are ICs which have been designed to do the downloading or it can be done under processors control. This facility makes the upgrading of FGPA code in the field an option and this also opens up the route to reconfigurable circuits. Some FPGAs allow for sections to be reprogrammed on the fly. This is a denser option than FLASH as the SRAM cells need less transistors than the equivalent FLASH cell.

The array is made of small silicon fuses. They use real fuses which are blown by passing excessive current through them. This means they cannot be reprogrammed. They are not widely used, except in stuff like RAD hardened space rocket and satellites. Tends to be the most expensive option.

Silicon Costs
Costs are very low, especially compared to PCB costs and component costs of a logic implementation. For example an Altera EP1k10 device has a roughly contains 576 registers and 12,228 bits of SRAM. Assuming a usage of 90 % this gives 518 registers and 11,000 bits of RAM.

If the registers are just plain d-type flip flops, thats around 72 octal packages in equivalent gates in the space of a 144 pin TQFP, for the cost of around $15. Plus it will run much faster that any discrete TTL logic.


To program an FPGA a number of software tools are required. All the top silicon vendors provide their own kit, plus there is a lot of third party software vendors out there. Most of the third party stuff is too expensive to be considered for this article. All the toolsets comprise of roughly the following set to tools.

The compiler takes your description of the FPGA and converts it into something the rest of the tools can handle. The most used options these days are :

  • VHDL

VHDL and VERILOG are hardware description languages ( HDL ), somewhat akin to C. Both are supported by all the main vendors. Which you choose is really a question of religion, if you want a good dust up try posting VERILOG/VHDL stinks on one of the many HDL forums. I use VHDL cause thats what got cheapest first.

Schematic capture is still available for the recalcitrant hardware designer who can’t/ won’t use anything resembling code. But for big designs the HDLs rule the roost.

There are a number of older languages still kicking round which predate the modern HDLs. Examples are ABEL and PALASM.

Synthesizers, fitters,a assemblers etc
These take the output of the compiler stage and make it fit into the FGPA. They will also produce timing information, so that the simulators can do a proper job.

So you have written your 100k gate super dooper widget and put it into the hardware and amazingly enough it doesn’t work. Now what ? – here comes the simulator to the rescue. So the simulator allows the design to be tested as a piece of software. It allow stimulus to be applied to the inputs and provides a record of the outputs. It will also allow the probing of internal bits of the design that you can’t get to when it is in the hardware. Almost all simulators now provide a graphical view of the outputs and either a graphical input scheme or a scripting language to provide input stimulus.

Modern simulators will use HDLs to provide the test stimuluses, known as a testbench.

Modelsim and Leonardo Spectrum are pretty well the industry standard, but deep pockets are generally required. Sometimes these are available as part of silicon vendors package at the right sort of price for me. But beware that sometimes these allegiances can be temporary affairs.

VHDL Simili is a low cost ( FREE ish ) VHDL only simulator that provides a good compromise for people lacking deep pockets. The completely free version is restricted in performance and design size.

Both Xilinx ( Webpack ) and Altera (Quartus ) provide complete design systems for free. And very good they are too. They offer a limited range of device types and sizes. If you want the very latest, biggest and fastest devices be prepared to get out your wallet. But for hobbyists and small companies they are a perfect solution.

Programming OK so you have got the design finished and polished by repeated simulation, so off to the real hardware. So how does it get there ?

Well some sort of programmer obviously, all the silicon guys will provide a PC based programmer – low cost ones run off the parallel port, more fancy ones use USB. Rolling your own is a route that can be followed, see here for a connection diagram. The parallel port versions are pretty simple affairs.

Another solution is to roll the programmer into the design. For instance a 5 pins of micro controller will program a RAM based devices. If the design is hanging off a PC, use the PC to control the downloading.

Learning Resources

As usual the web knows all. There are many excellent resources on the web for learning VHDL. Plus a whole industry of books available from all the normal places.

In addition there are style guides, example code, intellectual property – all only a google search away. A mere smattering of the useful sites can be found below.


FPGAs are now available and usable by anybody irrespective of size of the wallet. It is possible to do professional FPGA design without spending a penny on design tools or programming gear.

Links and things

Xilinx – one of the top two silicon vendors – toolsets, programmers and devices.
Altera -the other one.
Tools ( See above as well )
vhdl Simili – excellant low cost vhdl simulator
Accolade VHDL reference – loads of reference stuff
Dulous FPGA design site – loads of reference stuff and tutorials
VHDL Verification Course – Tutorial on test benches.
VHDL-Online – Tutorial on starting with VHDL, test benches etc
Libraries and IP
FMF Home Page – Free Model foundry
Free IP cores @ open cores – VHDL models
CorePool About CorePool – More models.
The hamburg archive of VHDL stuff – all flavours of vhdl stuff

Review of the Microchip ICD2 Programmer/Debugging Tool

Thursday, November 19th, 2009


This is a quick and dirty review of the Microchip ICD2 debugging and programming device for Microchip PIC processors. ICD2 offers relatively high end debugging features such as break points and triggers on very low end PIC processors for a very low cost

What Do You Get ?

A small round colourful widget with various holes around it for connecting to the target system and a PC. icd2Plus various bits of paper which show how and what to do to allow ICD2 to connect to the target hardware. The software comes on a CD and there is a not quite upto date version of the MicroChip MP LAB.


First make sure you have newish version of the MP LAB IDE installed and working on the target system. Then as long as follow the instructions it works straight out of the box. Be especially careful if you are using the USB option with the order of plugging in and loading of drivers. This is a real RTFM moment.


The ICD can operate either as an in-circuit programmer or as an in-circuit debugging tool. The device list covers most of the PICs and dsPICs, unfortunately the popular 16F72, 16F73, 16F74, 16F76, 16F77, 16F83 and 16F84A are not supported.
For use as a general purpose programmer Microchip offer an additional header with a ZIF socket and some jump leads, or the ICD can be used as an in-circuit programmer.
For debugging the ICD uses the programming interface to communicate with logic embedded in the target device. Thus the number of break points and the facilities available are determined by the target device.

Minor Gripes

The debugging a faulty module to target interface is not easy. The ICD cannot seem to discriminate between ‘not connected at all’, ‘connected and not running’ or ‘slightly connected’.
The target device must capable of being up and running code for the ICD to work. For example the PIC must be being clocked and not be in reset.
The ICD system uses some code and register space.
Two pins on the target device have to be allocated to the ICD during debugging.
We made our own cable to connect from the ICD2 to the target PCB, using a 6 pin telephone cable at one end and a simple 0.1″ pitch 6 way header at the other.
There seems to be a mode where the ICD2 refuses to allow debugging. The fix seems to be making the first 4 locations of EEPROM = 0x01,0x02,0x03,0x04. This can cause problems if your target code over writes these locations by design or mistake.
When used with the CCS C compiler there are restrictions on breakpoint locations in code. We often resorted to adding in “do nothing code” to get the breakpoint where expected.
Its not as real time as it seems. We found that its usage it debugging RS232 ports for example was limited.


Despite the above caveats this a very useful piece of kit for the hobbyist and small electronics company. It would justify its place on my bench just as an in-circuit programmer, the additional debugging facilities on offer being an excellent bonus.
For the cost ( current price is £85 +VAT) it is difficult to find fault.

Useful links


Review Of The CCS PIC C compiler

Thursday, November 19th, 2009


CCS produce a number of PIC related products including a range of C compilers:
PCB supports PIC16C5X
PCM supports PIC16C6X, 7X, 77X, 8X, 8XX & 9X
PCW supports both the above with a CCS specific IDE.
This review is specifically about the PCM compiler used in anger on a PIC16F877 project.

What Do You Get ?

A small package including a floppy disc and a manual.


We used the Microchip MPELAB IDE to edit and download programs to the target devices. So first make sure you have newish version, version 6 or better, of the MPE LAB IDE installed and working on the target system.
Then go to the CCS web site and download the MPE LAB Plugin. Next install the CCS compiler from floppy or CD then finally the MPELAB Plugin.
When you next fire up MPELAB the CCS compiler will be available in the toolsets menu for a new project.


Too many to mention them all. But some highlights are –
Some fancy footwork with the stack to allow many subroutine calls.
Loads of library routines for things like RS232 ports, ADCs, PWMs, in fact all the hardware bits of the supported PICs.
All the normal C lib stuff like printf.
Variable types include BIT and BYTE.
Interrupt handling library routines.
In line assembler code.
Loads of source code and examples for loads of different functions and interfaces.


When integrated into MPELAB the toolset is a joy, finish editing and a couple of clicks later the compiled code is on its way to the target device.
The provision of the hardware library routines means that you do not spend your time trying to debug hardware registers, just the logic of your code, you hit the floor running fast. This is a huge saving in time and energy.
If the ICD2 debugger is installed then the IDE is aware of breakpoints on C commands.

Minor Gripes

There are example start up files for all the supported device types, and it would be nice if one of these was chosen as a start place from the project start wizard. Finding them took a bit of digging around, as it wasn’t immediately obvious where they lived.
Some of the library functions, such as OUTPUT_HIGH and OUTPUT_LOW will not take variables as a parameter to a function. Work arounds are provided, but it is more messy than would at first appear necessary.
Double clocking to highlight or select a word sets the breakpoint. Very annoying at times.


I had huge reservations about how useful a C compiler could be for something as lowly as a 16F series PIC device. I was wrong. Anybody who is still messing around in assembler for the majority of the code is wasting their time.
There may be times when assembler code is really required, but the use of in line assembler will cover this eventuality. The time saving is enormous.
There are obviously games to be played with local and global variables in a devices with such limited resources, but these same restrictions apply to the assembler only route.
At a cost of around £100 this is top notch kit and put together with the ICD2 debugger forms a excellent PIC development system.

Useful links


One RF technology B868 Tiny Radio Module ( Tiny 112 )

Thursday, November 19th, 2009


tiny_112This is a review of the One RF technology B868 Tiny Radio Module, which is an FM radio MODEM. It is a half duplex FSK transceiver operating in the license free 868MHz ISM band. Also described are simple RF MODEM designs for connecting to an RS232 port and to a PC USB interface.


What you get is a module which is approx 32 x 19mm, with a integrated antenna covering the board circuitry.

Around three of the module edges are gold flashed connections to the internal circuitry. The module is designed to sit into a cutout of a PCB, although for breadboarding (accepting limited RF performance) it can just be wired to.

The module has a TTL level RS232 protocol interface through which data or AT commands may be passed. The module has additional pins, four of which can be configured as digital IO and two which are Analog to digital convector inputs.

Power requirements are modest, a total of 36mA at between 3V and 5.25V being required, through two filtered power pins. This falls to 4mA when the RF link is not active, and to 0.4mA when the module is in hardware standby.

The modules have several modes of operation, which are accessed through the AT command set. Modes are as follows:

  • Normal
  • where data arriving at the module RX pin is transferred to another modules TX pin
  • Secure
  • this mode is like normal mode expect that the data is packeted up and and gets acknowledged by the receiving device. This gives more data security.
  • Addressed
  • this allows the setting up of networks of modules. Each module is given a network number ( 0- 65535 ), which allows it to communicate with other modules with the same network number. Then within a network each module is given a unique ID( 0-255). Then data can be routed to a specific module by adding the module ID as a prefix. e.g. “002= fred” will send “fred” to module 002. Received messages have the source appended to the message. e.g. “004=fred” is a message from module 004.Note that here the datasheet is wrong as it implies that the message is terminated by a <CR>. In reality the message is terminated by a programmable timeout accessed through the AT command set.
  • IO Copy
  • this mode allows the state of the IO pins to be sent from a master module to a slave module.

Techie features

Well the datasheet has all the info, but a few of the headline facts.

Range – LOS upto 300m.
For best operating range a PCB with ground plane is recommended.
Data rate – 10kbits-1
Frequency – 868MHz

Things to be aware of

Not many actually, it does what it says it does, in the main.

Data sheet is inaccurate about message termination in address modes. It is a time out, not a character which terminates a message. This can have implications for throughput in this mode.

Getting into AT mode requires the use of some software as my hand cannot type the +++ sequence fast enough. I have used Teraterm with a simple script to do this.


A top notch piece of kit, easy and quick to get operational. If you want an RF link for project and can’t be bother with all the fuss of doing it yourself this is the way to go.

rf_modemDesign Ideas

By adding a regulator, a Max232 RS232 level shifter and a few discrete components a simple RS232 to RF MODEM adapter can be made.

See circuits below.



The PSU needs to be 6V with a current rating of least 200mA.

See here to purchase a PCB or kit of parts for the project.

Using the FTDI FT232BM USB chip a simple USB to RF MODEM can be designed. See circuits below.


FTDI drivers ( here ) for the device provide either a virtual COM port interface or an API DLL for coding with VB, VC, Delphi etc. Drivers are available for a wide range of operating systems, including all the usual suspects.

See here to purchase a suitable PCB or kit of parts for the project.

Useful links

RF Solutions UK distributor
One RF Technology Module manufacturer
FTDI USB interface chip manufacturers

Simple circuit serves as milliohmmeter

Thursday, November 19th, 2009

Simple circuit serves as milliohmmeter ( Published in EDN, 4/15/2004)